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The Fetch-Execute Cycle The von Neumann machine has a memory that stores both programs and data. Instructions are executed by reading an instruction, decoding it, and then executing it. All modern processors have accelerated the performance of von Neumann machines by overlapping operations by fetching the next instruction while the current instruction is being executed. We will omit this detail during our present discussion of the fetch execute cycle. A computer consists of relatively few building blocks. There are:
Let's walk through and instruction cycle. All von Neumann machines have a
program counter that contains the address of the next instruction to be
executed. An instruction cycle begins with the fetch phase where the instruction of read from memory. To do this, the contents of the program counter re copied to the memory address register that holds the address of data to be read from memory (or to be written into memory).
This diagram represents the structure of a primitive CPU. Click on it for a larger version. We can represent the first action in RTL form as. [MAR] ¬ [PC] picture
As soon as we read an instruction the contents of the program counter are incremented to point to the next instruction. If we assume that instructions are 32 bits, the increment is 4 (i.e, 4 bytes). That is, [PC] ¬ [PC] + 4 The next step is to use the address in the MAR and read the contents of memory at that location (this location contains the instruction we want). All memory data goes into the memory buffer register, MBR. We express this as [MBR] ¬ [[MAR]] picture The instruction is now in the memory buffer register and must be copied to the instruction register where it is decoded. This action is [IR] ¬ [MBR] At this stage, we've captured an instruction and the program counter is
pointing at the next instruction to be executed. What happens now depends on the
instruction we've just fetched. This computer interprets the bit pattern and
executes it. Lets assume that there are three instructions in memory that implement the operation Z = X + Y. We can represent this by the following three-instruction sequence (we are assuming a 2-address instruction format). MOVE R0,X Read the value of X
from memory and put in register R0 Let's look at how these instructions are executed, one by one. We give the fetch cycle with the first instruction but do not repeat it for each instruction. 1. MOVE R0,X {MAR]
¬ [PC] 2. ADD R0,Y [MAR]
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[IRaddress] Copy the
operand address to the MAR 3. MOVE Z,R0 [MAR]
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[IRaddress] Copy the
operand address to the MAR We have now executed three machine level instructions.
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If the program counter contains the value 1000, it means that the next
instruction is to be read from memory location 1000. 
