The RISC Challenge 

A new buzzword in computer architecture arose in the 1980s, RISC. The accepted definition of RISC is reduced instruction set computer, although term regular instruction set computer would be more appropriate. In practice, there is no such thing as a pure RISC processor – the term RISC simply describes a general historic trend in computer architecture that stresses speed and simplicity over complexity 

The RISC represented a major change in direction in the computer architecture world when it first appeared and many observers expected the RISC processor to sweep away all CISC processors like the 8086 and 68000 families. In practice, pure RISC processors didn't sweep away these CISC families. The characteristics of processors that are described as RISC are: 

• ·         register-to-register architecture

• ·         regular instruction set

• ·         pipelined organization (instruction execution is overlapped in time).

• ·         one clock cycle per instruction. 

The origins of RISC go back to John Cocke at the IBM research center in Yorktown Heights, NY, in the mid 1970s when IBM was working on the 801 project in an attempt to improve the cost/performance ratio of computers. IBM later used the experience gained in the 801 project when it developed its PC RT system for small workstations in engineering and scientific applications. The RT chip had some of the characteristics or RISC architectures but was fabricated in relatively old MOS technology and clocked at only 6 MHz. Consequently, the RT chip was not a commercial success, although it laid the foundations for the more successful PowerPC. 

It was the work carried out by David Paterson at the University of Berkley in the early 1980s that brought the RISC philosophy to a wider audience. Paterson was also responsible for coining the term "RISC" in a paper he wrote in 1980. 

The Berkeley RISC is an interesting processor for many reasons. Although it was constructed at a university (like many of the first mainframes such as EDSAC), the Berkeley RISC required only a very tiny fraction of the resources consumed by these early mainframes. Indeed, the Berkeley RISC is hardly more than an extended graduate project. It took about a year to design and fabricate the RISC I in silicon. By 1983 the Berkeley RISC II had been produced and that proved to be both a testing ground for RISC ideas and the start of a new industry.

The Berkeley RISC was later transformed into a commercial product, the SPARC architecture which is one of the few open architectures in the microprocessor world. An architecture is open if more than one manufacturer can produce it (this is not the same as second-sourcing where a company licenses another company to manufacture its product). 

By 1986 about ten companies were marketing processors described as RISCs. 

RISC architectures were quite controversial in the 1980s, partially because the large processor manufacturers were being told that they had been getting it wrong for the last few years and partially because a lot of the impetus for the RISC came out of universities rather than industry. 

It is important to emphasize that at least two developments in semiconductor technology made RISC possible. The first was the development of low-cost high-speed memory. When memory is very expensive, complex instructions make great sense. A complex instruction allows you to do a lot of computing for very little stored code. Consider the 68020's instruction BFFFO ([12,A0],D1*4,8),{D4:D5},D0. This remarkably powerful and complex instruction generates an effective address by adding 12 to the contents of pointer register A0, reading the pointer at that address and then adding 4 times the contents of data register D1 plus 8 to the pointer. The byte at this effective address provides the starting point for a bit field whose length is in D5 and whose location is the number of bits in D4 from bit 7 of the effective address. Finally, the processor scans the specified bit field and returns the location of the first "1" in the bit field in D0. If there's a more complex CISC instruction than this, I'd be interested to see what it is. 

This CISC instruction does a massive amount of computation and is specified in relatively few bits. Carrying out the same operation with simple instructions would require a much larger instruction space and hence increase system cost if memory is very expensive. 

The second development that made RISC architectures possible was the increase in bus widths. An 8-bit architecture can optimize instruction space by implementing 8-bit, 16-bit, and 24-bit instructions. Since RISC processors have register-to-register architectures, their instructions require at least log₂(op_codes) + 3log₂(registers). If we assume a system with 32 registers and 265 instructions, the minimum instruction size is log₂256 + 3log₂32 = 8 + 15 = 23 bits. 

Another early 32-bit RISC project was managed by John Hennessy at Stanford University. Their processor was called MIPS (microprocessor without interlocked pipeline stages). In the UK, Acorn Computers (Now ARM Ltd) designed the 32-bit ARM processor that we covered earlier in this book. Unlike The Berkeley RISC and MIPS, the ARM processor has only 16 registers and uses the instruction space freed up by requiring only 3 x 4 = 12 register address bits to provide a flexible instruction set that allows every instruction to be conditionally executed. We now describe two important second-generation RISC processors – the DEC Alpha and the PowerPC.  

The DEC Alpha

Having dominated the minicomputer market with the PDP11 and the VAX series, Digital set up a group to investigate how the VAX customer base could be preserved in the 1990s and beyond – the Alpha. According to a special edition of Communications of the AMC devoted to the Alpha architecture (Vol. 36, No 2, February 1993), the Alpha was the largest engineering project in Digital’s history. This project spanned more than 30 engineering groups in 10 countries.  

The group decided that a RISC architecture was necessary (hardly surprising in 1988) and that its address space should break the 32-bit address barrier. Unlike some of the companies that had developed earlier microprocessor families, DEC adopted a radical approach to microprocessor design – they thought about what they wanted to achieve before they started making silicon. As in the case of IBM’s System/360, Digital decoupled architecture from organization is order to create a family of devices with a common architecture but different organizations (they had already done this with the PDP11 and VAX architectures). 

Apart from performance and a life span of up to 25 years, DEC’s primary goals for the Alpha were the ability to run the OpenVMS and Unix operating systems and to provide “an easy migration path” from VAX and MIPS customer bases [Sites93]. Digital were far sighted enough to think about how the advances that had increased processor performance by a factor of 1,000 in past two decades might continue in the future. That is, Digital thought about the future changes that might increase the Alpha’s performance by a factor of 1,000 and allowed for them in their architecture. In particular, Digital embraced the superscalar philosophy with its multiple instruction issue. Moreover, the Alpha’s architecture was specifically designed to support multiprocessing systems. 

The Alpha has a linear 64-bit virtual address space and address segmentation is not used. The Alpha’s registers and data paths are all 64 bits wide. Digital did, however, make a significant compromise in the organization of the Alpha’s register file. Instead of providing general-purpose registers, the Alpha has separate integer and floating-point registers. Separating integer and floating-point registers simplified the construction (i.e., organization) of the chip set. Each register set contains 32 registers. Sites [Sites93] discusses the decision to provide 32 registers and concludes that more registers would increase chip complexity without significantly increasing the performance (in any case, adding more registers increases the time it takes the operating system to perform a context switch when it switches between tasks). 

Because the Alpha architecture was designed to support multiple instruction issue and pipelining, it was decided to abandon the traditional condition code register. Branch instructions test an explicit register. If a single CCR had been implemented, there would be significant ambiguity over which CCR was being tested in a superscalar environment. 

Digital’s Alpha project is an important milestone in the history of computer architecture because it represents a well thought out road stretching up to 25 years in the future. 

PowerPC 

The PowerPC was the result of a joint effort between IBM, Motorola, and Apple. Essentially, IBM provided the architecture, Motorola fabricated the chip, and Apple used it in their range of personal computers. 

IBM was the first company to incorporate RISC ideal in a commercial machine, the 801 minicomputer. The 801 implemented some of the characteristics of RISC architectures and its success led IBM to develop more powerful RISC architectures. IBM created their POWER architecture for use in their RS/6000 series workstations. The POWER architecture had RISC features, superscalar instruction issue, but retained some traditional CISC features such as complex bit manipulation instructions. Furthermore, POWER also provided single-instruction multiple register transfers between the register file and memory. 

A consortium of IBM, Motorola and Apple engineers took the POWER architecture and developed it into the PowerPC family of microprocessors. As in the case of Digital’s Alpha architecture, the PowerPC was designed to allow for future growth and a clear distinction was made between architecture and implementation. The POWER’s architecture was somewhat simplified and any architectural features that stood in the way of superscalar dispatch and out-of-order execution were removed. The architecture was also extended to provide a 64-bit superset. 

The first member of the PowerPC architecture was the 601 that was originally designed my IBM and modified by Motorola to include some of the facilities of Motorola’s own RISC device, the 88110. Some of the later members of the PowerPC family were the 603 (a low-cost, low-power processor aimed at the personal computer and laptop market), the 604 (a high-performance version aimed at both personal computers and workstations), and the 620 (a 64-bit version aimed at the server and workstation markets). 

We are now going to return to a more detailed discussion of the most successful of the personal computers, the IBM PC. This machine was to link together the fate of three organizations: IBM, Intel, and Microsoft.